Three agents for chip design.
Architect joins your RTL-to-GDS toolchain as a coordinating reasoning layer. It does not replace EDA tools, it directs the loop that runs them.
One agent per phase. Structured handoffs carry state forward.
Layout passes DEF to Verify. Verify returns an annotated violation list. Refine closes what it can and escalates the rest.
.v / .sv
.sdc
.lef
.def
placed.def
routed.def
prelim.spef
violations.json
timing.rpt
Layout Agent
The Layout Agent takes the synthesis netlist, timing constraints and starting floorplan definition, then runs the place-and-route engine end to end. It predicts global routing congestion, places macros against power intent and seeds clock tree synthesis before passing the placed and routed DEF onward.
- Synthesis netlist (.v / .sv)
- Timing constraints (.sdc)
- Technology LEF (.lef)
- Floorplan DEF (.def)
- Placed and routed DEF
- Early SPEF parasitics
- Congestion map
- Clock tree topology
Verify Agent
The Verify Agent applies DRC, LVS and static timing analysis to Layout Agent output. It produces a structured violation list with cell coordinates, severity scores and affected timing paths. Each item carries a root-cause annotation, rather than only a rule number, giving the Refine Agent and human reviewer the reason behind it.
- DRC per PDK rule deck
- LVS netlist/layout match
- STA setup and hold margins
- Power rail IR drop estimate
- Cell coordinates and layer
- Severity classification
- Root cause annotation
- Affected timing paths
Refine Agent
The Refine Agent reads the annotated violation report and sorts each item by remediability. It immediately patches auto-fixable issues by changing cell placement or via type. Heuristic-retry issues prompt constraint relaxation or tightening, followed by a run of the affected sub-region. Items needing human judgment are escalated with full context, giving the engineer a diagnosis instead of a raw error.
Runs beside your EDA tools. Reads native formats.
Architect does not replace your P&R licenses. It coordinates through the same file formats and drives the tools your team already uses.
.v / .sv.sdc.lef / .def.spef.libviolations.jsonReady for the agent pipeline on your next design?
Early access is capped at five active design teams. We work through your first real tape-out flow together.