In 2010, a custom ASIC tape-out at a commercial foundry typically needed 30 to 40 engineers: RTL designers, physical design engineers, verification specialists, DFT engineers, analog specialists for I/O cells, a tape-out coordinator, and foundry relationship management. EDA licenses alone cost several million dollars per year. A 40nm mask set cost between $1 million and $3 million. For a team of fewer than two dozen people, the work was out of reach without substantial venture funding or a large customer contract covering the expense.
That calculation has changed substantially. With the right tools, a suitable foundry program, and a tightly controlled design scope, a five-person team can reach tape-out at 28nm today. The change came in stages, and it is not finished. Teams deciding whether custom silicon fits their hardware product need to know which barriers fell and which ones remain.
Three Changes That Enabled Small-Team Tape-Out
Three changes developed in parallel over roughly a decade, lowering the barrier enough to matter for small teams.
The first was the rise of multi-project wafer (MPW) programs and shuttle services. MPW programs place multiple designs on one wafer and spread the mask set's fixed cost among customers. Instead of buying an entire mask set, which could cost several million dollars at advanced nodes, a small design can join a shared tape-out program for a fraction of that amount. TSMC CyberShuttle, IMEC's silicon program through Europractice, and similar foundry-specific shuttles now offer access routes that were not practical for small teams before 2015.
The second was the growth of accessible PDK and standard cell library ecosystems. The SkyWater 130nm open-source PDK, released with Google and Efabless in 2020, followed by the Caravel harness framework, showed that a complete ASIC flow could run on an open-source base without a proprietary EDA license. For production-quality work, TSMC and GlobalFoundries have also built more direct PDK access paths for smaller customers, without the relationship overhead common in foundry access ten years ago. The PDK barrier is lower, but it remains.
The third was broader access to cloud-based EDA tools. Cadence and Synopsys commercial P&R tools can now be obtained through subscription or usage-based cloud pricing. That removes the multi-year EDA site license as a mandatory fixed cost for serious physical design. A small team can charge EDA compute time to a specific tape-out program instead of maintaining permanent infrastructure. Each run costs more than an owned license, but the upfront capital need is much lower.
What Open PDKs Changed in Practice
SkyWater and similar open-source flows did more than reduce cost. They trained a generation of hardware engineers on a complete, production-quality physical design flow without proprietary infrastructure. An engineer who taped out with the Caravel harness at 130nm understands RTL-to-GDS, can identify and fix DRC violations, and has used post-layout parasitic extraction. That person can enter a 28nm commercial engagement with skills once limited largely to engineers from large chip companies.
The open-source ecosystem also encouraged tooling around those flows. OpenROAD, KLayout, and related tools emerged alongside PDK access. They are not production-equivalent to commercial P&R tools at advanced nodes, but they cover a substantial part of the flow. This creates an accessible training ground and increases the number of engineers able to contribute to production chip design on smaller teams.
The Barriers That Remain
Tape-out complexity below 28nm has not materially declined. The TSMC 16nm foundry design rule deck contains thousands of interacting rules. Metal fill, CMP density requirements, stress modeling for timing-critical transistors, and an expanding set of electrical rule checks all add layers to physical design. Better tools make these checks somewhat faster, not conceptually simpler.
DFT, or design for test, requirements have not become lighter either. A production ASIC at any commercial foundry requires scan chain insertion, boundary scan, and some level of built-in self-test. These support foundry acceptance testing as well as field diagnostics. DFT engineering is separate from physical design, and a five-person team usually lacks that skill internally. The choices are a DFT contractor, a design service company for that part of the flow, or a chip with limited testability. Each affects cost and schedule, so the choice belongs in the plan rather than appearing during tape-out preparation.
Analog and mixed-signal work remains a major obstacle for small teams. Custom I/O cells, PLLs, ADCs, and bandgap references need analog expertise and extensive simulation across multiple corners. When a product needs mixed-signal content beyond what licensed IP cores can provide, that expertise must come from somewhere. For most small-team ASIC programs, the practical answer is to keep the custom silicon digital-only and use proven silicon IP for analog functions.
We are not saying small teams cannot handle complexity. We are saying that advanced node DRC, DFT, and mixed-signal design have not become easier, and those are precisely the areas where a small team can hit a wall near tape-out, when fixes cost the most. Planning starts with separating the parts of the complexity curve that flattened from those that remain steep.
A 28nm Team Structure That Works
From what we have seen in teams working through the 28nm tape-out process, programs that reach tape-out without a dramatic team increase tend to share a few traits.
They keep the design scope narrow. A first 28nm tape-out works for a small team when it has one clearly defined function, a specific performance target, and no more than one or two large macro blocks. Multi-block SoC designs with eight or more IP integrations can work for experienced small teams, but they are not a sensible first tape-out at an advanced node. As block count rises, each engineer's complexity-management burden grows faster than the engineering workload itself.
They set up the EDA flow before RTL freeze. Teams that finish within the planned number of iterations have usually run a pilot P&R pass on part of the netlist, confirmed correct integration of the cell library and process technology files, and resolved flow configuration problems before schedule pressure arrives. The pilot takes three to five engineering days. Finding the same configuration problem on the first full P&R run takes weeks.
They budget EDA access as a variable cost. With cloud-based EDA licensing, compute time is a direct expense. A team that runs P&R overnight only when needed and closes unnecessary interactive sessions spends materially less than one that treats compute as free. That difference matters in bootstrapped programs, where compute budget is a real constraint.
Custom silicon is more accessible than it was. It is not easy. In small-team tape-out programs, the teams that plan accurately are the ones that distinguish access from simplicity before setting the schedule.