Three engineers covering a chip's physical design cannot reproduce a 20-person verification group by working longer hours. At an early-stage Cambridge-area AI chip startup, our layout team may own place-and-route, signoff, and tape-out coordination at the same time. The answer is not fewer checks. We place each check in one of three tiers: unattended automation, automation with an engineer-controlled gate, or referral to a specialist. That classification shows where tools can carry the load and where judgment must remain in the loop.
Misclassify a check in either direction and the schedule suffers. Automating a judgment call creates false confidence, while manually supervising a mechanical check consumes time the team needs elsewhere.
DRC and LVS: Clean Automation
DRC and LVS are ideal candidates for unattended execution. Their inputs and rules are defined, and their results are fundamentally pass or fail. That makes them poor uses of engineer attention during the run itself.
Schedule DRC and LVS jobs overnight, publish results to a shared dashboard, and review violations in the morning. Engineers should investigate the findings, not sit beside a terminal waiting for a deterministic process to finish.
The gate is simple: DRC and LVS must be fully clean before signoff. Small teams sometimes push an open DRC violation into STA to preserve momentum. That usually moves the same problem into a more expensive debugging cycle.
Antenna and ERC: Run in Order
Antenna checks look for charge accumulation risks during fabrication, while ERC checks electrical and connectivity conditions that ordinary geometry checks may miss. Both rely on defined rules rather than subjective interpretation.
Automate both, but preserve the order: run DRC, then antenna analysis in that same cycle, then LVS. If antenna repair inserts diodes, LVS must see those changes rather than compare against an earlier layout state.
STA: Automate Execution, Review the Meaning
STA sits between mechanical automation and engineering judgment. Launching the analysis is repeatable; deciding what its timing results mean requires knowledge of constraints, modes, paths, and design intent.
Automate signoff-corner setup, every required PVT corner, SPEF and SDC loading, the overnight run, and a morning summary. A small team should wake up to exceptions and trends, not a checklist of commands to execute.
"Negative slack on 12 paths" is not enough information to choose a gate. Those paths may be duplicate reports, constrained exceptions, or a real hold problem at the fast-fast corner. The engineer must establish which interpretation applies.
Keep a reviewed exception list with an owner, rationale, affected corner, and expiry condition. The practical STA gate is zero unreviewed negative slack, not zero negative slack. Every remaining exception should be understood and deliberately accepted.
Formal Verification for High Risk
Full-design formal verification usually scales beyond a three-person layout team's available time. Escalate selectively, starting with blocks whose failure would carry the highest functional or schedule risk.
For physical design teams, the most practical formal method is equivalence checking between RTL and the synthesis netlist after every netlist change. An ECO that alters the netlist without formal LEC can introduce a mismatch that survives until tape-out, when correction is far more costly.
Start by scripting LEC, or Logic Equivalence Check, between RTL and the synthesis netlist after each netlist change. Most EDA suites include this capability, and it requires less setup than proving a full set of formal properties.
Small Team Coverage Limits
No level of automation closes every coverage gap for a three-person team. The team can make physical signoff disciplined, but structural limits still matter.
Functional simulation coverage is the largest gap. It requires scenarios, stimulus, scoreboards, assertions, regressions, and enough observation of state space to expose behavior that DRC, LVS, STA, antenna, and ERC cannot see. A layout team building that program from scratch cannot do so while also completing physical design.
Three practical responses exist: hire a verification contractor, use the IP vendor's testbench and collateral, or reduce the functional state space through targeted design choices. None is complete by itself. Naming the option in use, its scope, and its remaining exposure is more useful than implying that automation solved the problem.
Physical signoff remains necessary: a clean DRC, LVS, STA, antenna, and ERC record means the layout team has completed its physical responsibility correctly. Calling physical signoff complete is not the same as claiming full functional verification. Keeping those claims separate prevents surprises at integration and tape-out.