Discovery timing decides whether a DRC violation is a three-minute fix or a three-week delay. A minimum metal spacing error found during interactive layout editing can be fixed in three minutes. Found at sign-off, after the foundry's DRC deck checks the complete GDS, the same error can delay tape-out for three weeks. The physical defect is unchanged. The cost depends on when it is found and what moved after it was created.
Most chip teams understand that basic relationship. The underestimate is usually in the second- and third-order effects: a re-route that removes the DRC error but creates new timing paths, the timing closure run those paths demand, and the organizational work of handling an ECO cycle while a foundry submission is under pressure. Fixing one DRC violation directly costs little. Finding it late can cost much more overall.
How DRC Problems Spread Through the Flow
At late stages, DRC violations generally fit into two classes with very different cost profiles. The first is local: a minimum spacing error between adjacent nets in a dense routing area, or a metal width violation at an isolated cell output. These can be corrected in place by changing the geometry of the offending wire or via. They do not disturb neighboring nets, move cells, or change timing relationships in nearby paths. A local violation found at sign-off still costs time through the engineering fix and an LVS re-run to confirm that connectivity did not change, but it does not cascade.
The second class is structural. Examples include a minimum area rule on a net that must move to another layer, a via density rule requiring fill vias in an already congested region, or an electrical rule check requiring cell buffer insertion to provide enough drive for a long wire. These cannot be resolved without changing routing across a region. That change brings new net lengths, new parasitics, and possible timing violations on paths sharing routing resources with the affected net. A structural violation fixed at sign-off therefore has a high probability of requiring at least one timing closure re-run.
When DRC Is Found
The cost curve for a DRC violation is non-linear. As discovery moves through the flow, both the repair effort and the number of downstream checks required afterward increase.
Found during P&R: the P&R tool automatically re-routes the affected net through design-rule-aware routing. No engineer intervention, downstream impact, or sign-off schedule effect is needed. Cost: only the added compute time for re-routing.
Found during the post-route DRC check, before sign-off: an engineer locates the error, applies a manual fix or changes a routing constraint, re-runs the affected region, and runs DRC again on the affected die area. If the change affects timing on paths using the re-routed net, STA must also be re-run for the affected timing corners. Cost: two to eight engineer-hours plus tool runtime.
Found at foundry sign-off submission: the foundry's DRC deck covers more checks than the in-house deck and can find errors the internal checks missed. The team must re-open the GDS, make the correction, run the full sign-off DRC deck again, re-run LVS, and re-run sign-off STA. When the fix touches a structural net, a full sign-off timing analysis re-run is mandatory. Cost: one to three weeks added to the tape-out schedule, plus a resubmission fee if the foundry charges for re-submission slots.
Found after mask tape-out, during a wafer re-spin: internal and external DRC checks missed the violation, and the mask set was submitted. Electrical testing after wafer return finds a functional failure traced to the DRC error. Cost: the mask set fee again, in the range of several hundred thousand dollars for advanced nodes, fabrication run time of eight to fourteen weeks, and the schedule delay. A well-run sign-off check should catch this, so it is rare, but not impossible.
The Main Sources of Late DRC Errors
Sign-off DRC findings are concentrated disproportionately in a few areas. Hierarchical boundary crossings, where separately routed blocks come together at the top level, are the most common source. Each block can pass DRC on its own, while assembly creates new minimum spacing errors between nets from different blocks that sit next to each other in the combined floorplan. At block-level DRC, those errors were hidden because the nets lived in different DEF files.
ECO cells are the second common source. When a functional bug calls for a late-stage cell insertion or net re-route, ECO routing often selects the shortest available path instead of the cleanest geometric path. The ECO tool prioritizes connectivity, not design-rule compliance in nearby regions. An ECO net routed under schedule pressure is therefore a dependable source of DRC errors that remain unseen until the next full DRC run.
Metal fill is the third source. Density rules require metal fill on most advanced nodes, and fill is added late in the flow. If the fill algorithm's spacing parameters are not tuned to the foundry's deck, the new fill can create minimum spacing errors with existing routing nets.
Coordination Costs More Than the Re-Route
The actual routing change for a late structural DRC violation usually takes a few hours of engineering work. The weeks come from coordinating everything around it. The affected block owner must review the fix. The timing closure lead must review the post-fix timing analysis. The sign-off DRC re-run must fit the team's EDA license allocation. LVS must be re-run and verified. If timing analysis exposes a new error caused by the fix, the cycle begins again.
That coordination explains how three hours of engineering work can consume two weeks of calendar time. The engineering tasks can run in parallel, but review and sign-off pass through senior engineers who must decide that the fix is correct and that the design is ready for re-submission.
Late-stage DRC discovery is not automatically catastrophic. A local violation with no timing effect can carry manageable coordination overhead. The issue is that most DRC prevention cost models count engineering work while ignoring the calendar time spent coordinating it. Calendar time on a tape-out schedule carries a different cost from engineering-hours, and that coordination burden is what makes late DRC discovery genuinely expensive.
What Prevention Looks Like on Real Flows
Continuous DRC checking during P&R, instead of one check at sign-off, delivers the largest cost reduction for the effort involved. P&R tools can perform incremental DRC checks after each routing pass and try automatic re-routing before violations compound. Used consistently rather than only at checkpoints, these capabilities keep the violation count near zero throughout P&R. The remaining errors are the genuinely difficult ones that automation cannot resolve, which is the useful distribution: human attention goes to hard violations rather than easy errors an earlier automated check would have found.
For hierarchical designs, run block-boundary DRC against a hypothetical assembly before signing off the individual blocks. This means creating a partial assembly DEF containing only the boundary regions of adjacent blocks, then running DRC on that file. It is not a standard item on most tape-out checklists, but it catches the category most disproportionately expensive to discover at sign-off.
The arithmetic behind early DRC investment remains consistent: more comprehensive checks during P&R, plus fixes made when they take hours instead of weeks, require less time than late discovery. Prevention feels like extra work while the team is already busy, whereas late-stage DRC cost is visible and immediate. That cost asymmetry explains why teams systematically underinvest in prevention.